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LC72725KVS
Input/Output Data Format
TEST
0
0
1
1
MODE
0
1
0
1
Circuit Operation Mode
Master read out mode
Slave read out mode
Standby mode (crystal oscillator stopped)
IC test mode which is not available to user applications.
RDCL Pin
Clock output
Clock input
-
-
RDS-ID/READY Pin
RDS-ID output
READY output
-
-
RST Pin
RST = 0
RST = 1
Master mode
Slave mode
Normal operation
RDS-ID ? demodulation circuit clear + READY ? memory clear (when slave mode)
RDS-ID/READY Pin
RDS-ID output (Active-high)
READY output (Active-high)
Note: RDS-ID(READY) pin is an n-channel open-drain output, and requires an external pull-up resistor to output data.
RDCL/RDDA Output Timing in Master Mode
RDCL output
RDDA output
RDS-ID Output Timing
17 μ s Tp21
421 μ s
421 μ s
Tp1
17 μ s
RDS-ID
High/Low
High/Low
High/Low
High/Low
High/Low
High/Low
High/Low
RDCL
RDDA
Note: RDS-ID is High: data with high RDS reliability, Low: data with low RDS reliability
No.A1744-6/9
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